Measurement-computing TempScan/1100 Manual de usuario descargar pdf (Pagina 114)

5-24 System Operation

889897

TempScan / MultiScan User's Manual

The Event Status Enable Register (

ESE

) controls which events, if any, are to be reflected in the Status Byte

STB). The bits of the Event Status Register (ESR) are logically ANDed with the corresponding

bits of the

ESE, and the resulting bits are logically ORed together in the Status Byte Register (STB). The

ESE does not affect the ESR; it only affects the ESR Bit 5 (or ESB) of the STB. The ESR Bit 5 (or ESB) in

the

STB is set when its corresponding Bit 5 in the Service Request Enable Register (SRE) is enabled. The

ESE is set and interrogated with the Set Event Mask (N) command. For more information, see command Set

Event Mask (

N) in the chapter API Command Reference.

Service Request Enable Register (SRE)

The Service Request Enable Register (

SRE) is a Read/Write/Clear register in that it can be written and

cleared, as well as read by the controller, via the Set SRQ Mask (M) commands –

M?, Mmask, and M0,

respectively.

The Service Request Enable Register (

SRE) may be used to define those conditions in the Status Byte

STB) which will generate a Service Request (SRQ). The bits in the SRE represent an exact image

of the bits in the

STB except for the Request for Service Bit (RQS, Bit 6) or Master Summary Status Bit

(

MSS, Bit 6). When a condition is set in the STB, its image bit is checked in the SRE. If the image bit is

enabled, the TempScan/1100 or MultiScan/1200 will generate a Service Request (

SRQ).

The Service Request Enable Register (

SRE) controls which bits of the Status Byte Register (STB) are

reflected in the Request for Service Bit (

RQS, Bit 6) and Master Summary Status Bit (MSS, Bit 6) of the

STB. The bits of the STB are logically ANDed with the corresponding bits of the SRE. The resulting bits are

logically ORed together to form the Master Summary Status Bit (

MSS, Bit 6) in the STB and to control the

Request for Service Bit (

RQS, Bit 6) in the STB. The SRE does not affect the STB; it only affects the MSS

and

RQS Bits of the STB. The ESE is set and interrogated with the Set SRQ Mask (M) command. For more

information, see command Set SRQ Mask (

M) in the chapter API Command Reference.

Using Status-Reporting Registers

As previously mentioned, the status-reporting registers are organized in a hierarchical structure. The lower-

level registers contain more-general event information, and the higher-level registers contain more-detailed

information about particular events. Typically, the lowest-level status-reporting register, the Status Byte

STB) contains time-critical information that may require more immediate action from the

controller. In addition, other registers may access the

STB via the ESR Bit (or ESB). This allows any

condition within the status-reporting register hierarchy to have access to the

STB

, Serial Poll (

SPOLL

), and

Service Request (

SRQ).

Example 13g. Status-Reporting Register Hierarchy

(1)

PRINT#1, “OUTPUT07;N0 X N8 X”

(2)

PRINT#1, “OUTPUT07;M0 X M32 X”

(3)

PRINT#1, “OUTPUT07;E?X”

(4)

PRINT#1, “ENTER07”

(5)

INPUT A$

E008

(6)

PRINT#1, “OUTPUT07;U2X”

(7)

PRINT#1, “ENTER07”

(8)

INPUT A$

E002

(9)

PRINT#1, “OUTPUT07;U0X”

(10)

PRINT#1, “ENTER07”

(11)

INPUT A$

E000

(12)

PRINT#1, “SPOLL07”

The above example demonstrates how the status reporting register hierarchy works. Notice that clearing of

the higher-level registers clears the bits in the lower-level registers that were associated with the root cause

of the condition.

1 2 ... 109 110 111 112 113 114 115 116 117 118 119 ... 305 306

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