Measurement-computing CIO-DAS800 Manual de usuario descargar pdf (Pagina 15)

Table 4-3. Bit Definitions

* Asterisk indicates that HCEN is required (as a final step) to make

this bit functional.

Digital Output bits

OP4:1

Digital Input bits.

IP3:1

Channel-scan end value

EC2:0*

Channel-scan start value.

SC2:0*

0 if HCEN =0. 0 if HCEN =1 & FIFO not empty. Undefined if HCEN = 1 and FIFO

empty

FF3*

0 if HCEN =0. 0 if HCEN =1 & FIFO not empty. Undefined if HCEN = 1 and FIFO

empty

FF2*

FIFO Overflow (full) =1. 0 if HCEN =0.

FFOV*

FIFO Empty =1. 0 if HCEN =0.

FFEM*

State of Digital Trigger (1=Trigger occured)

DT*

Enable Interrupt on FIFO Half Full (Req. IEOC=1, HCEN must =1 to enable

FIFO)

ENHF*

(N/A)

R3:0

CS1:0

CSE

Internal Time Base (8254) Enable

ITE*

Cascade AD Pacing Mode Enable (include CT/2)

CASC*

External Digital Trigger Enable (Edge trig if GTEN=0)

DTEN*

Interrupt Source (1 = End of Convert, 0 = Ext)

IEOC

Enable Auto channel-scan

EACS*

Gate Enable (Req. DTEN to enable HW gate)

GTEN*

Hardware Convert Enable

HCEN

End-of-conversion (1 = busy, 0 = ready)

EOC

Interrupt enable (0 = disable, 1 = enable)

INTE

Mux address bits

MA2:0

Analog data input (Read low byte first)

AD 11:0

DEFINITIONS:

1 2 ... 10 11 12 13 14 15 16 17 18 19 20

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