
CIO-DAS1401/12User's Guide Specifications
17
Counters
Table 3. Counter specifications
3 down counters, 16-bits each
Counter 0 — Independent, user
configurable
Source: Programmable - Internal 100 kHz or external (CTR0
Clock)
Gate: External (DIN2)
Output: Available at user connector (CTR0 Out)
Counter 1 — ADC Pacer Lower Divider
Source: 1 or 10 MHz oscillator (jumper selectable)
Gate: Tied to CTR2 Gate, programmable source.
Output: Chained to CTR2 Clock.
Counter 2 — ADC Pacer Upper Divider
Source: CTR1 Out
Gate: Tied to CTR1 Gate, programmable source.
Output: Programmable as ADC Pacer clock, hardwired to user
connector (CTR2 Out)
High pulse width (clock input)
Low pulse width (clock input)
Power consumption
Table 4. Power consumption specifications
Environmental
Table 5. Environmental specifications
Operating temperature range
Storage temperature range
Main connector and pin out
Table 6. Main connector specifications
Compatible accessory products with the
C37FF-x cable
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