Measurement-computing CIO-DAC04/12 Manual de usuario descargar pdf (Pagina 11)

1 SIMUL DAC Simultaneous update mode. All DAC's are updated when Channel 3 is updated.

= 0 Normal DAC update mode (as data comes in).

= 1 Simultaneously updates all four DAC's when Channel 3 accessed.

2,3 Not Used

4-6 INT# Selects Interrupts 2-7.

INT2 INT1 INT0 IRQ selected

0 0 0 None

0 0 1 None

0102

0113

1004

1015

1106

1117

7 INTE Interrupt Enable.

= 0 Interrupts disabled (default).

= 1 Interrupts enabled.

Status Register Description (Read Base + 3)

Bit #

Name Description

0 INTST Interrupt flip-flop status. Clocked high when FIFO goes

less than half-full. Requires active pacer gate, does not require Interrupt enable.

(Resets interrupt)

1 FFERR FIFO Error Status. Goes high if FIFO went empty during pacing. Valid only while

pacer clock is active. (Resets FIFO).

2 FFHF FIFO Half Full. Low when FIFO has 512 samples or more.

3 FFE FIFO Empty. Low when FIFO is empty.

4-6 INT# Reads Selected Interrupt.

7 INTE Interrupt Enable

Base + 4 (Digital Input / Output)

RD DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0

WR DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0

Base + 5 ----------------------------------------------- NOT USED ---------------------------------------------

Base + 6 ----------------------------------------------- NOT USED ---------------------------------------------

Base + 7 ----------------------------------------------- NOT USED ---------------------------------------------

-7-

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 17 18

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Measurement-computing CIO-DAC04/12 Manual de usuario Pagina 11